Area-efficient, reduced and no-snapback PNP-based ESD protection in advanced Smart Power technology

A new approach, based on reduced and no-snapback components, was studied to face high-voltages I/Os severe ESD specifications. An accurate physical analysis of the mechanisms encountered during ESD stresses drove to define the parameters controlling the snapback and the high current R_ON, and then to quantify the attainable performances. For the first time in Smart Power technologies, design rules are drawn to take full advantage of self-biased PNP for efficient high voltages protections. TLP characterizations have confirmed the high potentialities of PNP.