DocumentCode :
502676
Title :
ESD: Standards, threats and system hardness fallacies
Author :
Hyatt, Hugh
Author_Institution :
Hyger Physics, Inc. 6411 Cedar Terrace Lane NW, Bremerton, WA 98312, USA
fYear :
2002
fDate :
6-10 Oct. 2002
Firstpage :
178
Lastpage :
185
Abstract :
It is a fallacy to assume equipment meeting ESD standards will automatically result in products immune to environmental ESD. Some ESD Standards do not generate threat levels typical of environmental ESD events and therefore do not insure survivability of the final product. Comparing environmental ESD threat voltages and ESD standardized testing levels outlines the major environmental ESD risk to electronic systems.
Keywords :
Character generation; Circuit testing; Computer aided manufacturing; Consumer electronics; Electronic equipment testing; Electrostatic discharge; Integrated circuit testing; Physics; System testing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
2002 Electrical Overstress/Electrostatic Discharge Symposium, 2002. EOS/ESD '02.
Conference_Location :
Charlotte, NC, USA
Print_ISBN :
978-1-5853-7040-5
Electronic_ISBN :
978-1-5853-7040-5
Type :
conf
Filename :
5267025
Link To Document :
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