Cache optimization for real time MPEG-4 encoder

Due to the speed up of the VLSI technology, the high speed of the DSP core is not compatible with much lower speed external memory. The low speed of the off-chip memory, which is mainly responsible for the DSP delays, all that was called memory wall. The memory wall seriously confined the DSP´s computation capability for the intense data exchange algorithm. This paper provides two strategies (Regulation the L2 cache, adjust the encoding procedure) to speed up the performance of the Cache which based on the study of the architecture of the TMS320DM642 two level cache and the algorithm flow of the MPEG-4 encoder.