A scheduling algorithm for maintaining packet order in fully buffered multistage switching fabric

With the fast development of transport technology and the constantly increasing Internet traffic, the multi-stage switching fabric will be the next step for scalable routers in next generation network. Nevertheless, current memory-space-memory (MSM) Clos switching fabric exhibits poor performance under unbalanced traffic. By taking buffers into the internal links of switching fabric, this paper proposes an alternative fully buffered three-stage Clos switching fabric - FBC, which not only could provide perfect throughput performance, but also exhibits a better delay performance in heavy load by storing cells at the internal buffers. To resolve the issue of packet disorder, this paper also provides a scheduling algorithm for maintaining packet order - Load-balance and token-ring based scheduling algorithm (LTS) for FBC. This algorithm is based on the load-balance at central-stage and token-ring scheduling between central-stage and output-stage which is prone to implement in hardware at the promise of maintaining packet order. At last, the simulation results prove that LTS is more effective.