SOI lateral diode optimization for ESD protection in 130nm and 90nm technologies

Author

Salman, Akram ; Beebe, Stephen ; Pelella, Mario ; Gilfeather, Glen

Author_Institution

Adv. Micro Devices, Sunnyvale, CA, USA

fYear

2005

fDate

8-16 Sept. 2005

Firstpage

1

Lastpage

7

Abstract

We study the SOI poly-defined lateral diode and its optimization to achieve high second breakdown current, low resistance and low capacitance. A second breakdown current of more than 12 mA/mum is achieved. We present a novel failure mechanism for the diode wherein oxide breakdown occurs during a CDM-like event; floating the poly gate is shown to reduce this susceptibility. We also introduce a biasing method for a gated diode that reduces loading capacitance without impacting ESD performance.

Keywords

capacitance; electrostatic discharge; semiconductor device breakdown; semiconductor diodes; silicon-on-insulator; ESD protection; SOI lateral diode optimization; biasing method; breakdown current; capacitance loading reduction; failure mechanism; size 130 nm; size 90 nm; Capacitance; Cathodes; Diodes; Electric breakdown; Electrostatic discharge; Implants; Protection; Pulse measurements; Silicon on insulator technology; Thermal resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium, 2005. EOS/ESD '05.

Conference_Location

Tucson, AZ

Print_ISBN

978-1-58537-069-6

Electronic_ISBN

978-1-58537-069-6

Type

conf

Filename

5271713