Title :
Evaluation on board-level noise filter networks to suppress transient-induced latchup under system-level ESD test
Author :
Ker, Ming-Dou ; Hsu, Sheng-Fu
Author_Institution :
Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
Different types of board-level noise filter networks are evaluated for their effectiveness to improve the immunity of CMOS ICs against transient-induced latchup (TLU) under system-level electrostatic discharge (ESD) test. By choosing proper components in each noise filter network, the TLU immunity of CMOS ICs can be greatly improved. All the experimental evaluations have been verified with the SCR test structures and the ring oscillator fabricated in a 0.25-mum CMOS technology. Some of such board-level solutions can be further integrated into the chip design to effectively improve TLU immunity of CMOS IC products.
Keywords :
CMOS integrated circuits; electrostatic discharge; filters; immunity testing; integrated circuit design; integrated circuit noise; integrated circuit reliability; integrated circuit testing; CMOS IC products; CMOS technology; ESD; SCR test structures; board-level noise filter networks; chip design; ring oscillator; size 0.25 mum; system-level electrostatic discharge test; transient-induced latchup; CMOS technology; Diodes; Electrostatic discharge; FETs; Filters; FinFETs; MOS devices; Manufacturing; Silicon; System testing;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2005. EOS/ESD '05.
Conference_Location :
Tucson, AZ
Print_ISBN :
978-1-58537-069-6
Electronic_ISBN :
978-1-58537-069-6
