DocumentCode
503013
Title
A study of relation between a power supply ESD and parasitic capacitance
Author
Suzuki, Teruo ; Iwahori, Junji ; Morita, Teruo ; Takaoka, Haruyoshi ; Nomura, Toshio ; Hashimoto, Kenji ; Ichino, Shoji
Author_Institution
Macro Dev. Dept., FUJITSU VLSI Ltd., Kasugai, Japan
fYear
2005
fDate
8-16 Sept. 2005
Firstpage
1
Lastpage
8
Abstract
In this study, we show that increased parasitic capacitance across lateral NPN (LNPN) devices does not necessarily enhance the electro-static discharge (ESD) robustness. Since the drain-bulk displacement current decreases, the LNPN avalanche trigger current increases and the PN junctions fail early. In our case, this happened when the parasitic capacitance between supply lines is around many hundreds of Pico-Farad.
Keywords
bipolar transistors; electrostatic discharge; power supply circuits; PN junctions; drain-bulk displacement current; lateral NPN devices; parasitic capacitance; power supply ESD; Electrostatic discharge; Parasitic capacitance; Power supplies;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium, 2005. EOS/ESD '05.
Conference_Location
Tucson, AZ
Print_ISBN
978-1-58537-069-6
Electronic_ISBN
978-1-58537-069-6
Type
conf
Filename
5271780
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