Title :
Analysis of ESD protection components in 65nm CMOS technology: Scaling perspective and impact on ESD design window
Author :
Boselli, Gianluca ; Rodriguez, John ; Duvvury, Charvaka ; Smith, Jeremy
Author_Institution :
Silicon Technol. Dev., Texas Instrum. Inc., Dallas, TX, USA
Abstract :
A scaling analysis of fundamental ESD components (low voltage transistors, N-well diodes, interconnects and thin dielectrics) for the last three CMOS technology nodes (130 nm, 90 nm and 65 nm) targeting the same low-power applications is presented. The impact of technology scaling on the ESD design window will be discussed.
Keywords :
CMOS integrated circuits; electrostatic discharge; low-power electronics; scaling circuits; CMOS technology; ESD design window; ESD protection; low-power applications; scaling circuit; size 130 nm; size 65 nm; size 90 nm; CMOS technology; Dielectrics; Electrostatic discharge; Instruments; Integrated circuit interconnections; Isolation technology; Protection; Silicidation; Silicon; Voltage;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2005. EOS/ESD '05.
Conference_Location :
Tucson, AZ
Print_ISBN :
978-1-58537-069-6
Electronic_ISBN :
978-1-58537-069-6
