ESD protection for advanced CMOS SOI technologies

Author

Khazhinsky, Michael G. ; Stockinger, Michael ; Miller, James W. ; Weldon, James C.

Author_Institution

Freescale Semicond., Inc., Austin, TX, USA

fYear

2005

fDate

8-16 Sept. 2005

Firstpage

1

Lastpage

10

Abstract

In this paper we describe a 90 nm SOI ESD protection network and design methodology including both device and circuit level characterization data. We compare TLP results of SOI MOSFETs and diodes to bulk devices. We present a new response surface method to optimize device sizes in the ESD networks and show circuit level data comparing TLP test results and SPICE simulation results of an I/O test circuit. We also present product test data for standard ESD stress models.

Keywords

CMOS integrated circuits; MOSFET; SPICE; circuit testing; electrostatic discharge; nanoelectronics; silicon-on-insulator; ESD network; ESD protection; I/O test circuit; SOI MOSFET comparison; SPICE simulation result; Si-SiO₂; TLP test result; advanced CMOS SOI technology; device size optimization; response surface method; size 90 nm; standard ESD stress model; CMOS technology; Circuit testing; Design methodology; Diodes; Electrostatic discharge; MOSFETs; Optimization methods; Protection; Response surface methodology; SPICE;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium, 2005. EOS/ESD '05.

Conference_Location

Tucson, AZ

Print_ISBN

978-1-58537-069-6

Electronic_ISBN

978-1-58537-069-6

Type

conf

Filename

5271822