Active-area-segmentation (AAS) technique for compact, ESD robust, fully silicided NMOS design

Author

Keppens, Bart ; Mergens, Markus P J ; Armer, John ; Jozwiak, Phillip C. ; Taylor, Gordon ; Mohn, Russ ; Trinh, Cong Son ; Russ, Christian C. ; Verhaege, Koen G. ; De Ranter, Frederic

Author_Institution

Sarnoff Eur., Gistel, Belgium

fYear

2003

fDate

21-25 Sept. 2003

Firstpage

1

Lastpage

9

Abstract

This paper describes a layout technique to optimize the ESD performance per area for fully silicided NMOS devices by segmenting the active area of drain and source regions. Efficient multi finger triggering is achieved by intrinsic inter-finger-coupling through the bulk enabled by compact finger design. The technique is successfully applied in a 0.13 um and a 0.18 um CMOS technology obtaining HBM ESD capability of up to 8.6 V/um².

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit layout; CMOS; ESD performance optimisation; HBM ESD; active-area-segmentation technique; compact finger design; intrinsic inter-finger-coupling; layout technique; multifinger triggering; silicided NMOS design; size 0.13 mum; size 0.18 mum; CMOS technology; Costs; Electronic ballasts; Electrostatic discharge; Europe; Fingers; MOS devices; Protection; Robustness; Silicides;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium, 2003. EOS/ESD '03.

Conference_Location

Las Vegas, NB

Print_ISBN

978-1-5853-7057-3

Electronic_ISBN

978-1-5853-7057-3

Type

conf

Filename

5272015