Title :
TLP analysis of 0.125 μm CMOS ESD input protection circuit
Author :
Chaine, Michael ; Davis, James ; Kearney, Al
Author_Institution :
Micron Technol., Inc., Boise, ID, USA
Abstract :
In this investigation, TLP ESD analysis shows that if a large input resistor is used in combination with a ggNMOS clamp in the input protection circuitry, then the trigger voltage, Vt1, of the ggNMOS increases. More importantly, the HBM injected current required to trigger snapback, It1, is significantly increased which unexpectedly delays the trigger of the ggNMOS secondary clamp and exposes the input receiver´s thin gate oxide to excessive input pad stress voltages which results in 1-2 kV HBM leakage failures.
Keywords :
CMOS integrated circuits; clamps; electrostatic discharge; CMOS ESD input protection circuit; ESD snapback clamp; HBM leakage failures; TLP ESD analysis; electrostatic discharge; ggNMOS clamp; human body model; input pad stress voltages; input receiver thin gate oxide; large input resistor; size 0.125 mum; transmission line pulse; voltage 1 kV to 2 kV; Breakdown voltage; CMOS technology; Circuit synthesis; Circuit testing; Clamps; Electrostatic discharge; Failure analysis; MOS devices; Protection; Resistors;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2003. EOS/ESD '03.
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-5853-7057-3
Electronic_ISBN :
978-1-5853-7057-3
