3D integration with AC coupling for wafer-level assembly

This paper presents a solution of stacked chips using a capacitive communication from electrodes at the last metal layer with a wafer level assembly process. The wafer level approach instead of the die level allows high throughput and enables further optimization of the capacitive structures. To reach a good AC coupling an additional passivation layer was deposited then planarized and at the same time the dielectric thickness was monitored. An inter-electrode oxide around 400 nm was proved and then bonded by molecular direct bonding. The alignment accuracy of plusmn1 mum and the bonding quality were checked by infrared microscopy. The upper silicon wafer was thinned around 50 mum. The buried I/O pads of both chips were opened by dry plasma etching through the back of the top wafer. The stacked chips were diced and packaged in a standard ceramic cavity and bonded with gold wires. Good performance in term of low power and a large communication bandwidth of 1.23 Gbps/pin with 8times8 mum² electrodes has been measured.