Impact of package parasitics on the EMC performance of smart power SoCs

Author

Merlin, Marco ; Fiori, Franco

Author_Institution

Ist. Superiore Mario Boella, Torino, Italy

fYear

2009

fDate

15-18 June 2009

Firstpage

1

Lastpage

6

Abstract

The paper deals with the propagation of EMI in Smart Power SoCs through high frequency parasitic paths, i.e. silicon substrate, and it focuses on the interaction between on-chip parasitic capacitors and package parasitic elements, that negatively affects IC electromagnetic emission. The paper highlights such unwanted parasitic effects through computer simulations and experimental test results. Finally, a new grounding scheme to improve the EMC performance of such integrated circuits is presented.

Keywords

electromagnetic compatibility; electromagnetic interference; power integrated circuits; system-on-chip; EMC; EMI; IC electromagnetic emission; SoC; on-chip parasitic capacitors; package parasitic elements; silicon substrate; smart power; Capacitors; Circuit testing; Computer simulation; Electromagnetic compatibility; Electromagnetic interference; Electromagnetic propagation; Frequency; Grounding; Integrated circuit packaging; Silicon; electromagnetic emission; package parasitics; smart power; substrate grounding; switching noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Packaging Conference, 2009. EMPC 2009. European

Conference_Location

Rimini

Print_ISBN

978-1-4244-4722-0

Electronic_ISBN

978-0-6152-9868-9

Type

conf

Filename

5272977