Analog multiplier for a low-power integrated image sensor

This paper presents a new approach to an integrated low-power and low-cost image sensor design. A matrix multiplier is proposed as a better alternative to known massively parallel architectures. The circuit, although less flexible in number of possible to implement algorithms, characterizes very low power consumption and occupied chip area. The presented circuit is designed using 0.35 mum two polysilicon, three metal CMOS technology. It consumes about 8 mW of supply power and occupies 15 mm² including photoreceptor matrix. A similar solution based on a massively parallel architecture needs 250 mW of supply power and occupies 40 mm² of chip area.