Title :
Conduction error reducing at power FET´s linear model extraction
Author :
Kapralova, A.A. ; Manchenko, L.V. ; Pchelin, V.A.
Author_Institution :
Fed. State Unitary Corp. R&PC Istok, Fryazino, Russia
Abstract :
The simple method of error reduction of contacting in the process of regenerating of analog circuits of power FETs is presented. The technique is based on the measuring operation of the same transistor in 50 Ohm line and than in the matching circuit with the specified impedance.
Keywords :
analogue processing circuits; electric impedance imaging; power field effect transistors; analog circuit regenerating process; conduction error reduction; impedance matching circuit; power FET linear model extraction; resistance 50 ohm; Circuits; FETs; Helium; Organizing;
Conference_Titel :
Microwave & Telecommunication Technology, 2009. CriMiCo 2009. 19th International Crimean Conference
Conference_Location :
Sevastopol
Print_ISBN :
978-1-4244-4796-1
