• DocumentCode
    503808
  • Title

    A Simulation Times Model of Multi-core Simulation

  • Author

    Yu, Zhibin ; Jin, Hai ; Hu, Yabin

  • Author_Institution
    Services Comput. Technol. & Syst. Lab., Huazhong Univ. of Sci. & Technol., Wuhan, China
  • Volume
    1
  • fYear
    2009
  • fDate
    19-21 May 2009
  • Firstpage
    7
  • Lastpage
    11
  • Abstract
    Chip multi-processor (CMP) increases processor throughput by duplicating resources for many threads. Due to the main frequency of a single processor approaching to limit, CMP is becoming more and more popular. However, it is not well studied how to evaluate a new CMP design by simulation. This paper analyzes the possible organizations of cores on a CMP and then presents a mathematical model for the simulation times. It also provides a sampling policy used to reduce the simulation times. The sampling experiments show that the simulation time is 7.5 days under condition that the required confidence level is 95% and confidence interval is 4 when the benchmarks in SPEC CPU2000 are used. As for the simulation of CMPs, the simulation time is very short.
  • Keywords
    microprocessor chips; multi-threading; multiprocessing systems; virtual machines; SPEC CPU2000; chip multiprocessor; confidence interval; confidence level; multicore simulation; processor throughput; sampling policy; single CMP; Analytical models; Computational modeling; Computer simulation; Frequency; Hardware; Multicore processing; Process design; Sampling methods; Throughput; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Software Engineering, 2009. WCSE '09. WRI World Congress on
  • Conference_Location
    Xiamen
  • Print_ISBN
    978-0-7695-3570-8
  • Type

    conf

  • DOI
    10.1109/WCSE.2009.372
  • Filename
    5318891