DocumentCode
50497
Title
Ferroelectric-Assisted Dual-Switching Speed DRAM–Flash Hybrid Memory
Author
Rajwade, Shantanu R. ; Naoi, Taro A. ; Auluck, Kshitij ; Jayant, Krishna ; Van Dover, R.B. ; Kan, Edwin C.
Author_Institution
Sch. of Electr. & Comput. Eng., Cornell Univ., Ithaca, NY, USA
Volume
60
Issue
6
fYear
2013
fDate
Jun-13
Firstpage
1944
Lastpage
1950
Abstract
This paper presents a novel one-transistor low-voltage DRAM-Flash hybrid memory. The proposed device integrates ferroelectric thin film and nonvolatile charge injection, and demonstrates two modes of operations: 1) a fast (10-100 ns) DRAM mode with ~ 103 s of retention, associated with ferroelectric switching, and 2) a slower (0.1-1 ms) Flash mode with long retention time, from charge tunneling into the floating nodes. The time evolution of the electric field in the ferroelectric and the tunnel oxide is shown to naturally establish the two-step mechanism during the program operation. The complementary characteristics of ferroelectric switching and gate-charge injection enable low-voltage program/erase (±8 V), reasonable memory window (0.8 V), and long retention time. Devices were fabricated with the lead zirconatetitanate thin film as the ferroelectric layer and Au nanocrystals for gate-injected electron storage. Pulsed programming measurements were also performed to distinguish the memory window obtained from the two mechanisms in DRAM and Flash operations.
Keywords
DRAM chips; ferroelectric storage; ferroelectric switching; flash memories; low-power electronics; nanoelectronics; transistor circuits; tunnelling; Au; DRAM mode; DRAM operation; DRAM-flash hybrid memory; charge tunneling; complementary characteristics; electric field; ferroelectric layer; ferroelectric switching; ferroelectric thin film; ferroelectric-assisted dual-switching speed; flash mode; flash operation; floating node; gate-charge injection; gate-injected electron storage; lead zirconatetitanate thin film; low-voltage program; memory window; nanocrystal; nonvolatile charge injection; one-transistor low-voltage DRAM-flash; program operation; pulsed programming measurement; retention time; time 0.1 ms to 1 ms; time 10 ns to 100 ns; time evolution; tunnel oxide; voltage 0.8 V; DRAM–flash; dual speed; ferroelectric (FE); hybrid;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2013.2257787
Filename
6514542
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