Linearization of CMOS CCCII with optimal design via geometric programming

The mixed translinear loop, serving as the input stage of a CMOS CCCII, is analyzed in large signal method to examine the linearity condition, which is simply the matching between NMOS and PMOS loop components. Example configurations, providing linear and nonlinear V-I characteristic of input voltage and current, are simulated in the HSPICE based on the AMS´s 0.35mu CMOS process. The results verify the necessity of matching condition in designing a linear CMOS CCCII. To obtain an optimized design, the geometric programming is utilized based on attained perceptions. A sample requirement, also based on the AMS´s 0.35mu CMOS process, is globally optimized. The obtained solution is simulated in the HSPICE to verify the performances, which are satisfying the requirement quite well.