Thermal Design and Constraints for Heterogeneous Integrated Chip Stacks and Isolation Technology Using Air Gap and Thermal Bridge

This paper summarizes the thermal challenges in conventional 3-D stacks and proposes a novel stacking structure that eases the thermal problem. The objective of this paper is first to define limits and opportunities for developing different 3-D chip stacks from a thermal perspective, and second to explore our proposed system as a function of microbumps, through silicon vias, die thickness, and other design parameters. In our proposed 3-D stack, the interposer integrated microfluidic heat sink serves as the main heat sink. To thermally decouple stacked dice, we propose air gap isolation between them and a thermal bridge on top of the stack to cool down the isolated die. To evaluate the thermal benefits of the stack, a thermal model is developed based on the finite difference method. Several chip stack scenarios are studied and the simulations are conducted with a processor power of 74.63 W/cm² and memory power of 2.82 W/cm². The proposed architecture yielded processor and memory temperatures of 64°C and 40°C, respectively, compared with 76°C and 75°C for the air cooled stack.