Jitter tolerance estimation of a 3X oversampling CDR using event-driven simulation

This paper presents a system level jitter tolerance estimation of a 3X oversampling Clock and Data Recovery (CDR) circuit used in high speed serial data communication receivers. It is critical to know the amount of jitter that can be tolerated by the CDR in order to recover the data with satisfied bit error ratio (BER) performance. The jitter tolerance of the CDR is estimated by an event-driven simulation model, developed in Matlab. The theoretical jitter tolerance value is derived analytically for different jitter frequencies. The simulated results show a very close match to the theoretical values. We also compared the simulation time for the event-driven and the conventional fixed-time-step models.