CMOS distributed active power splitter with multiple-gated transistor linearization for ultra-wideband applications

In this paper, the design of a fully-integrated CMOS distributed active power splitter incorporating multiple-gated transistor linearization that allows for broadband distortion reduction is presented. Simulation results has yielded a peak S21 power gain of 7.8 dB and then rolls off to a unity gain bandwidth of 10.5 GHz with less than 5° phase imbalance and amplitude imbalance of less than 0.9 dB over the band. The simulation results show an 8.5 dB IIP3 improvement and a 10 dBc improvement at output power of −10 dBm. The proposed active power splitter has broadband signal transmission gain that compensates loss and was designed using the 0.13µm CMOS technology.