Title :
A 12-bit 10MS/s 2-stage algorithmic ADC in 130-nm CMOS utilizing capacitor sharing and capacitor scaling technique
Author :
Hai, N. ; Nairn, D.G.
Author_Institution :
Department of Electrical and Computer Engineering, University of Waterloo ON, Canada N2L 3G1
Abstract :
This paper presents a low power 12-bit 10MS/s algorithmic analog-to-digital converter (ADC) implemented in a 130-nm CMOS technology. A technique is proposed for using capacitor scaling and capacitor sharing to reduce the power requirements of algorithmic analog-to-digital converters. The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 66dB while consuming 1mW from a 1.5V supply.
Keywords :
Algorithmic analog-to-digital converter (ADC); capacitor scaling; capacitor sharing; low power; unit-multiplying digital-toanalog converter (U-MDAC);
Conference_Titel :
Microsystems and Nanoelectronics Research Conference, 2009. MNRC 2009. 2nd
Conference_Location :
Ottawa, ON, Canada
Print_ISBN :
978-1-4244-4751-0
