Design of a novel high-performance reduced clock-swing pre-discharge flip-flop

Reduced clock-swing flip-flops are very attractive in high-performance deep-pipelined systems since significant power reduction can be achieved with minimal performance degradation. In this paper, a new reduced clock-swing pre-discharge flip-flop (RCSPDFF) is proposed. The performance advantage of RCSPDFF comes from the fact that its critical path is reduced significantly to only four transistors in the worst case. A detailed comparison is carried out between the proposed RCSPDFF and previous published reduced clock swing flip-flops. Simulation results in the 65nm CMOS technology have shown that RCSPDFF is able to achieve much better performance with similar power dissipation than the previous proposed flip-flops, and thus resulting in a greater overall PDP reduction.