• DocumentCode
    505525
  • Title

    A DRC-based check tool for ESD layout verification

  • Author

    Smedes, T. ; Trivedi, N. ; Fleurimont, J. ; Huitsing, A.J. ; de Jong, P.C. ; Scheucher, W. ; van Zwol, J.

  • Author_Institution
    NXP Semicond., Nijmegen, Netherlands
  • fYear
    2009
  • fDate
    Aug. 30 2009-Sept. 4 2009
  • Firstpage
    1
  • Lastpage
    9
  • Abstract
    The growing complexity of IC designs makes verification for ESD correctness increasingly difficult. A useful verification tool, based on specific ESD layout rules and extended with layout connectivity, will be presented. The demonstrated approach is extendable with respect to checks and analysis options. Successful usage has been demonstrated on products.
  • Keywords
    electrostatic discharge; integrated circuit layout; DRC-based check tool; ESD correctness; ESD layout verification; IC designs; layout connectivity; Analytical models; Bipolar transistors; Breakdown voltage; Electrostatic discharge; Fault location; Information analysis; Inspection; Pins; Product design; Protection;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    EOS/ESD Symposium, 2009 31st
  • Conference_Location
    Anaheim, CA
  • Print_ISBN
    978-1-58537-176-1
  • Electronic_ISBN
    978-1-58537-176-1
  • Type

    conf

  • Filename
    5340112
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=505525