Technology scaling of advanced bulk CMOS on-chip ESD protection down to the 32nm node

Author

Li, Junjun ; Chatty, Kiran ; Gauthier, Robert ; Mishra, Rahul ; Russ, Christian

Author_Institution

IBM Semicond. R&D Center, Essex Junction, VT, USA

fYear

2009

fDate

Aug. 30 2009-Sept. 4 2009

Firstpage

1

Lastpage

7

Abstract

Technology scaling data are presented based on 65 nm, 45 nm, and the 32 nm high-K, metal gate process. Thin oxide NFET parasitic bipolar snapback and gate dielectrics breakdown voltages decrease to 3.2V and 3.6V, respectively. The top concern is to achieve adequate voltage clamping at I/O pads. Continuous improvement in ESD device failure currents per area is found. Vertical metal wiring schemes are needed to overcome wiring resistance challenges.

Keywords

CMOS integrated circuits; MOSFET; electrostatic devices; electrostatic discharge; failure analysis; semiconductor device breakdown; I/O pads; bulk CMOS on-chip ESD protection; complementary metal-oxide-semiconductor; electrostatic discharge; failure currents per area; gate dielectric breakdown voltage; gate-nonsilicided silicide-blocked NMOSFET; high-K metal gate process; input/output pads; metal-oxide-semiconductor field effect transistor; parasitic bipolar snapback; size 32 nm; technology scaling; thin oxide NFET; vertical metal wiring scheme; voltage clamping; wiring resistance; Breakdown voltage; CMOS technology; Clamps; Continuous improvement; Dielectric breakdown; Electrostatic discharge; High K dielectric materials; High-K gate dielectrics; Protection; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

EOS/ESD Symposium, 2009 31st

Conference_Location

Anaheim, CA

Print_ISBN

978-1-58537-176-1

Electronic_ISBN

978-1-58537-176-1

Type

conf

Filename

5340140