Whole-chip ESD protection design verification by CAD

Author

Lin, Lin ; Xin Wang ; Tang, He ; Fang, Qiang ; Zhao, Hui ; Wang, Xigang ; Zhan, Rouying ; Xie, Haolu ; Gill, Chai ; Zhao, Bin ; Zhou, Yumei ; Zhang, Gary ; Xigang Wang

Author_Institution

Dept. of Electr. Eng., Univ. of California, Riverside, CA, USA

fYear

2009

fDate

Aug. 30 2009-Sept. 4 2009

Firstpage

1

Lastpage

10

Abstract

CAD is essential to simulation, design and synthesis of on-chip ESD protection circuitry to ensure design prediction and verification at whole-chip level. This paper reviews a new function-based ESD CAD platform and design methodology, including arbitrary ESD protection device extraction algorithm, smart parametric ESD checking mechanism, smart ESD zapping simulation flow and new CAD tools enabling whole-chip ESD protection design verification. Practical design examples are presented.

Keywords

BiCMOS integrated circuits; CAD; electronic engineering computing; electrostatic discharge; BiCMOS; CAD; ESD protection device; design methodology; design verification; electrostatic discharge; extraction algorithm; on-chip ESD protection circuitry; smart ESD zapping simulation flow; smart parametric ESD checking mechanism; Algorithm design and analysis; Circuit simulation; Circuit synthesis; Design automation; Design methodology; Electrostatic discharge; Pins; Predictive models; Protection; Radio frequency;

fLanguage

English

Publisher

ieee

Conference_Titel

EOS/ESD Symposium, 2009 31st

Conference_Location

Anaheim, CA

Print_ISBN

978-1-58537-176-1

Electronic_ISBN

978-1-58537-176-1

Type

conf

Filename

5340146