An integrated memory management scheme for dynamic alias resolution

When a program object can be accessed via multiple names, an aliasing problem occurs. The existence of aliasing decreases the efficiency of register usage and increases the instruction bandwidth requirements because of the need to maintain the consistency among multiple copies of the object in the memory hierarchy. In this paper, a simple and efficient memory management scheme is developed to dynamically resolve aliasing problems. The scheme rests upon the integrated management of registers and on-chip data cache. With this support the compiler is able to make better use of processor registers without extra consistency maintenance overhead. Furthermore, unlike previous approaches this scheme does not require expensive associative search hardware, which potentially can lengthen the machine cycle time or the pipeline depth, and is shown to be equally applicable to multiprocessor configurations without modification.