Title :
More iteration space tiling
Author_Institution :
Oregon Graduate Center
Abstract :
Subdividing the iteration space of a loop into blocks or tiles with a fixed maximum size has several advantages. Tiles become a natural candidate as the unit of work for parallel task scheduling. Synchronization between processors can be done between tiles, reducing synchronization frequency (at some loss of potential parallelism). The shape and size of a tile can be optimized to take advantage of memory locality for memory hierarchy utilization. Vectorization and register locality naturally fits into the optimization within a tile, while parallelization and cache locality fits into optimization between tiles.
Keywords :
Frequency synchronization; Processor scheduling; Registers; Shape; Tiles;
Conference_Titel :
Supercomputing, 1989. Supercomputing '89. Proceedings of the 1989 ACM/IEEE Conference on
Conference_Location :
Reno, NV, United States
Print_ISBN :
0-89791-341-8
DOI :
10.1145/76263.76337