An efficient FPGA packing algorithm based on simple dual-output basic logic elements

Logic packing is an important procedure in an FPGA CAD flow. To get a more efficient mapping performance, a simple dual-output BLE based packing algorithm called WHUpakcer is presented. WHUpacker takes advantages of the dual-output BLE different from the popular one used in previous studies. This new BLE has a simpler and more refined architecture by contrast to the popular one and thus introduces a more efficient cluster mapping. Upon the experimental results on two sets of benchmarks, WHUpacker demonstrates better performance up to 12% than both P-TVpack and T-Vpack.