Title :
Architecturally-efficient computation of shortest paths for a mobile robot
Author :
Sridharan, K. ; Priya, T.K. ; Kumar, P. Roshan
Author_Institution :
Elec. Eng. Dept, IIT Madras, Chennai, India
Abstract :
The computation of shortest path for a mobile robot to get to a destination is considered in this paper. An architecturally-efficient solution is presented for this problem. Results of implementation in Xilinx Virtex FPGA are promising: the solution operates at approximately 72 MHz and the implementation for a graph with 40 nodes and 52 edges fits in one XCV3200E-FG1156 device.
Keywords :
field programmable gate arrays; mobile robots; path planning; XCV3200E-FG1156 device; Xilinx Virtex FPGA; frequency 72 MHz; mobile robot; shortest path computation; Costs; Educational institutions; Field programmable gate arrays; Hardware; Industrial electronics; Linear programming; Mobile robots; Navigation; Service robots; Very large scale integration; Architecture; FPGA; Mobile Robot; Shortest Path;
Conference_Titel :
Industrial Electronics & Applications, 2009. ISIEA 2009. IEEE Symposium on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-4681-0
Electronic_ISBN :
978-1-4244-4683-4
DOI :
10.1109/ISIEA.2009.5356447
