Title :
Using ant colony optimization for test vector reordering
Author :
Wang, Jianhua ; Shao, Jingbo ; Li, Yingmei ; Huang, Yuyan
Author_Institution :
Provincial Key Discipline & Key Lab., Harbin Normal Univ., Harbin, China
Abstract :
The increasing complexity of chip design has posed great challenge for low power SoC test. Test vector reordering technique can lower circuit power dissipation. This paper proposes a new approach to low power SoC test based on ant colony optimization to find the optimal orders for test vector application. Experimental results on benchmark ITC´02 demonstrate the average improvement of 12.3% over the existing methods.
Keywords :
automatic testing; integrated circuit testing; low-power electronics; optimisation; system-on-chip; ant colony optimization; chip design; low power SoC test; power dissipation; test vector reordering; Ant colony optimization; Circuit testing; Clocks; Computer science; Educational institutions; Electronic equipment testing; Industrial electronics; Laboratories; Power dissipation; System-on-a-chip; Ant colony algorithm; Test vector reordering;
Conference_Titel :
Industrial Electronics & Applications, 2009. ISIEA 2009. IEEE Symposium on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-4681-0
Electronic_ISBN :
978-1-4244-4683-4
DOI :
10.1109/ISIEA.2009.5356501
