Architecture of an embedded localization processor for underwater vehicle using FPGA

The computation of parallel problems by FPGA calls for mobile computing, that uses an array of independent, locally connected processing elements, or logic elements, which compute a problem in parallel technique. Computing cells determines FPGA-based computer performance according to the possible cell density and the speedup over computation of a conventional single processor. This design and the performance results of two new computing-cell architecture types are presented in this paper. DUPLICATED entails one cycle to perform all operations, and it takes the least amount of time but the most chip area. SINGLE-BOOTH performs the large multiplier unit in SINGLE and does all operations with a single W-bit adder using the BOOTH algorithm, which takes a longer time but allows a large cell density. The performance results of underwater localization and tracking case study show that the greatest speedup has been provided by DUPLICATED as compared to other types of architecture, but its usefulness is limited by its small cell density. Thus, the number of computing cells and the speed required determine the best architecture for a particular problem.