Title :
Parallel multi-level analytical global placement on graphics processing units
Author :
Cong, Jason ; Zou, Yi
Author_Institution :
Comput. Sci. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA
Abstract :
GPU platforms are becoming increasingly attractive for implementing accelerators because they feature a larger number of cores with improved programmability. In this paper, we describe our implementation of a state-of-the-art academic multi-level analytical placer mPL on Nvidia´s massively parallel GT200 series platforms. We detail our efforts on performance tuning and optimizations. When compared to software implementation on Intel´s recent generation Xeon CPU, the speed of the global placement part of mPL is 15× faster on average using a Tesla C1060 card, with comparable WL. (less than 1% WL degradation on average).
Keywords :
computer graphic equipment; coprocessors; parallel algorithms; GPU platforms; Intel recent generation Xeon CPU; Nvidia massively parallel GT200 series platforms; Tesla C1060 card; accelerators; coprocessor acceleration; graphics processing units; parallel multilevel analytical global placement; Acceleration; Algorithm design and analysis; Central Processing Unit; Circuit simulation; Degradation; Graphics; Iterative algorithms; Partitioning algorithms; Runtime; Simulated annealing; Circuit placement; Co-processor acceleration; GPU;
Conference_Titel :
Computer-Aided Design - Digest of Technical Papers, 2009. ICCAD 2009. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-60558-800-1
Electronic_ISBN :
1092-3152
