DocumentCode :
507436
Title :
Binning optimization based on SSTA for transparently-latched circuits
Author :
Gong, Min ; Zhou, Hai ; Tao, Jun ; Zeng, Xuan
Author_Institution :
Microelectron. Dept., Fudan Univ., Shanghai, China
fYear :
2009
fDate :
2-5 Nov. 2009
Firstpage :
328
Lastpage :
335
Abstract :
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transparent latches are widely used. In this paper, we formulate and solve the binning optimization problem that decides the bin boundaries and their testing order to maximize the benefit (considering the test cost) for a transparently-latched circuit. The problem is decomposed into three sub-problems which are solved sequentially. First, to compute the clock period distribution of the transparently-latched circuit, a sample-based SSTA approach is developed which is based on the generalized stochastic collocation method (gSCM) with Sparse Grid technique. The minimal clock period on each sample point is found by solving a minimal cycle ratio problem in the constraint graph. Second, a greedy algorithm is proposed to maximize the sales profit by iteratively assigning each boundary to its optimal position. Then, an optimal algorithm of O(n log n) runtime is used to generate the optimal testing order of bin boundaries to minimize the test cost, based on alphabetic tree. Experiments on all the ISCAS´89 sequential benchmarks with 65-nm technology show 6.69% profit improvement and 14.00% cost reduction in average. The results also demonstrate that the proposed SSTA method achieves an error of 0.70% and speedup of 110X in average compared with the Monte Carlo simulation.
Keywords :
Monte Carlo methods; circuit optimisation; computational complexity; graph theory; greedy algorithms; integrated circuit manufacture; microprocessor chips; stochastic processes; Monte Carlo simulation; SSTA; alphabetic tree; bin boundaries; binning optimization; clock period distribution; constraint graph; fabricated chips; generalized stochastic collocation method; greedy algorithm; high performance microprocessors; minimal clock period; minimal cycle ratio; optimal testing; sales profit; sparse grid technique; testing order; transparent latches; transparently-latched circuits; Circuit testing; Clocks; Cost function; Distributed computing; Greedy algorithms; Grid computing; Latches; Marketing and sales; Microprocessors; Stochastic processes; Binning Optimization; Latched Circuits; SSTA;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design - Digest of Technical Papers, 2009. ICCAD 2009. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
ISSN :
1092-3152
Print_ISBN :
978-1-60558-800-1
Electronic_ISBN :
1092-3152
Type :
conf
Filename :
5361271
Link To Document :
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