BIST design optimization for large-scale embedded memory cores

Built-in self test (BIST) is a crucial technique for testing embedded memory cores in a system-on-chip (SoC). However, there is not much published work on BIST design optimization for multiple memory cores in the SoC designs. In this paper, we present a method for the BIST design optimization problem for large-scale SoC embedded memory cores, considering various real-world constraints such as peak current, IR drop, etc. Our method is based on a three-stage technique: (1) assignment, (2) legalization, and (3) refinement. The first stage adopts an integer linear programming (ILP) formulation for each memory partition to find a desired assignment of memory cores to controllers. The second stage then legalizes the assignment to meet user-specified assignment constraints. The last stage refines the solution to further reduce its cost. Experimental results show that our method can reduce the test time by 26.6%, the routing length by 8.9%, and the area by 24.1%, compared with a heuristic method currently used in industry.