Solution Space Reduction of Simulated Evolution Algorithm for Solving Standard Cell Placement Problem

Author

Shiraishi, Yoichi ; Ono, Takaaki ; Dahb, Mona Abo El

Author_Institution

Dept. of Production Sci. & Technol., Gunma Univ., Ota, Japan

Volume

4

fYear

2009

fDate

14-16 Aug. 2009

Firstpage

420

Lastpage

424

Abstract

Simulated Evolution algorithm is versatile, efficient but very much time consuming. This paper shows that the reduction of trials in the allocation phase leads to the improvement of the performances of Simulated Evolution algorithm. In its application to the cell placement problem of VLSI chip, 90% reduction of the solution space in the allocation phase accelerates the total processing time, 4.6 ~ 7.7 times and improves the solution quality, 1.6 ~ 6.4% when compared with an exhaustive search of the solution space. This result is also useful for implementing Simulated Evolution algorithm on an FPGA.

Keywords

VLSI; circuit layout CAD; evolutionary computation; field programmable gate arrays; FPGA; VLSI chip; simulated evolution algorithm; solution space reduction; standard cell placement problem; Acceleration; Computational modeling; Cost function; Field programmable gate arrays; Genetic algorithms; Minimization; Production; Space technology; Stochastic processes; Very large scale integration; Accerelation; FPGA; Placement; Simulated Evolution; Solution Space; VLSI;

fLanguage

English

Publisher

ieee

Conference_Titel

Natural Computation, 2009. ICNC '09. Fifth International Conference on

Conference_Location

Tianjin

Print_ISBN

978-0-7695-3736-8

Type

conf

DOI

10.1109/ICNC.2009.681

Filename

5364483