Implementation of two dimensional pulse compression based on embedded processor in FPGA

This paper first analyses the technology characteristic of FPGA. An efficient two dimensional pulse compression processing system in which FPGA is the platform of signal processing and its embedded processor MicroBlaze is control kernel is designed and implemented using Xilinx´s XC2V6000FPGA. In the limit of resource in FPGA, two different implementation architectures of pulse compression are presented in terms of speed and area restrictions. A DDR SDRAM controller which is realized in FPGA carries out efficient matrix transposition processing under the way of matrix partition linear mapping. Further more, a simple SAR imaging processing is simulated in this FPGA system for validation.