An efficient digital down converter architecture for wide band radar receiver

This paper, the architecture and the implementation of an efficient digital down converter (DDC) processor for wide band radar receiver are presented. This architecture of the processor is based on the sampling technique in which the sampling frequency is 4 times as high as the intermediate frequency and the use of half band filter architecture. It avoids 3/4 the use of multiplications compared with the conventional architecture. The improved method decreases the complexity of computation, reduces the area and power of the processor. The efficient method is implemented in FPGA. Compared with the conventional method, resources are saved 82.78% and the power consumption is reduced about 100 mW. One design example is given and the results proved the validity and efficiency of the improved digital down converter architecture.