• DocumentCode
    509975
  • Title

    Preemptive Virtual Clock: A flexible, efficient, and cost-effective QOS scheme for networks-on-chip

  • Author

    Grot, Boris ; Keckler, Stephen W. ; Mutlu, Onur

  • Author_Institution
    Dept. of Comput. Sci., Univ. of Texas at Austin, Austin, TX, USA
  • fYear
    2009
  • fDate
    12-16 Dec. 2009
  • Firstpage
    268
  • Lastpage
    279
  • Abstract
    Future many-core chip multiprocessors (CMPs) and systems-on-a-chip (SoCs) will have numerous processing elements executing multiple applications concurrently. These applications and their respective threads will interfere at the on-chip network level and compete for shared resources such as cache banks, memory controllers, and specialized accelerators. Often, the communication and sharing patterns of these applications will be impossible to predict off-line, making fairness guarantees and performance isolation difficult through static thread and link scheduling. Prior techniques for providing network quality-of-service (QOS) have too much algorithmic complexity, cost (area and/or energy) or performance overhead to be attractive for on-chip implementation. To better understand the preferred solution space, we define desirable features and evaluation metrics for QOS in a network-on-a-chip (NOC). Our insights lead us to propose a novel QOS system called preemptive virtual clock (PVC). PVC provides strong guarantees, reduces packet delay variation, and enables efficient reclamation of idle network bandwidth without per-flow buffering at the routers and with minimal buffering at the source nodes. PVC averts priority inversion through preemption of lower-priority packets. By controlling preemption aggressiveness, PVC enables a trade-off between the strength of the guarantees and overall throughput. Finally, PVC simplifies network management through a flexible allocation mechanism that enables per-application bandwidth provisioning independent of thread count and supports transparent bandwidth recycling among an application´s threads.
  • Keywords
    microprocessor chips; network-on-chip; quality of service; QoS scheme; SoC; cache banks; core chip multiprocessors; link scheduling; memory controllers; networks-on-chip; preemptive virtual clock; quality-of-service; specialized accelerators; static thread; systems-on-a-chip; Bandwidth; Clocks; Communication system control; Costs; Network-on-a-chip; Quality of service; Recycling; System-on-a-chip; Throughput; Yarn; Design; Measurement; Performance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International Symposium on
  • Conference_Location
    New York, NY
  • ISSN
    1072-4451
  • Print_ISBN
    978-1-60558-798-1
  • Type

    conf

  • Filename
    5375384