Title :
A Tagless Coherence Directory
Author :
Zebchuk, Jason ; Qureshi, Moinuddin K. ; Srinivasan, Vijayalakshmi ; Moshovos, Andreas
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Abstract :
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based protocols, and therefore scale to a large number of cores. Unfortunately, conventional directory structures incur significant area overheads in larger CMPs. The tagless coherence directory (TL) is a scalable coherence solution that uses an implicit, conservative representation of sharing information. Conceptually, TL consists of a grid of small Bloom filters. The grid has one column per core and one row per cache set. TL uses 48% less area, 57% less leakage power, and 44% less dynamic energy than a conventional coherence directory for a 16-core CMP with 1MB private L2 caches. Simulations of commercial and scientific workloads indicate that TL has no statistically significant impact on performance, and incurs only a 2.5% increase in bandwidth utilization. Analytical modelling predicts that TL continues to scale well up to at least 1024 cores.
Keywords :
cache storage; data structures; memory protocols; microprocessor chips; Bloom filters; cache coherence; chip multiprocessors; directory structures; directory-based protocols; information sharing; snoop-based protocols; tagless coherence directory; Analytical models; Bandwidth; Coherence; Computational modeling; Filters; Performance evaluation; Permission; Predictive models; Protocols; Testing; Bloom Filters; Cache coherence; Directory Coherence;
Conference_Titel :
Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International Symposium on
Conference_Location :
New York, NY
Print_ISBN :
978-1-60558-798-1