Architecture design principles for the integration of synchronization interfaces into network-on-chip switches

Author

Ludovici, Daniele ; Strano, Alessandro ; Bertozzi, Davide

Author_Institution

Comput. Eng. Lab., TUDelft, Delft, Netherlands

fYear

2009

fDate

12-12 Dec. 2009

Firstpage

31

Lastpage

36

Abstract

This paper contributes to the maturity of the GALS NoC design practice by advocating for tight integration of GALS synchronization interfaces into NoC architecture building blocks. At the cost of re-engineering the input/output stages of NoC switches and network interfaces, this approach proves capable of materializing GALS NoCs with the same area and power of their synchronous counterparts, while reducing latency at the clock domain boundary. This design style is experimented in this paper with a mesochronous synchronizer and a dual-clock FIFO, which are tightly coupled with the switches of the xpipesLite NoC architecture.

Keywords

integrated circuit design; network-on-chip; switching circuits; synchronisation; GALS synchronization interface; architecture design principle; dual-clock FIFO; globally asynchronous locally synchronous clocking; mesochronous synchronizer; network-on-chip switch; synchronization interface integration; xpipesLite NoC architecture; Circuits; Clocks; Delay; Electronic design automation and methodology; Frequency synchronization; Hardware; Network-on-a-chip; Switches; Throughput; Timing; Dual-Clock FIFO; Globally Asynchronous Locally Synchronous; Mesochronous Synchronization; Networks-on-Chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Network on Chip Architectures, 2009. NoCArc 2009. 2nd International Workshop on

Conference_Location

New York, NY

Print_ISBN

978-1-60558-774-5

Type

conf

Filename

5375716