DocumentCode :
510010
Title :
Toward a science for future NoC design
Author :
Marculescu, Radu
Author_Institution :
Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear :
2009
fDate :
12-12 Dec. 2009
Firstpage :
1
Lastpage :
2
Abstract :
Traditionally, the design space exploration for systems-on-chip has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the design of the communication architecture plays a major role in defining the area, performance, and energy consumption of the overall system. From a technology point of view, this paradigm shift is meant to mitigate the problem of interconnects, keep the design complexity under control, and reduce costs. Since neither point-to-point, nor bus-based communication scale well in terms of power and performance figures, the network-on-chip architecture has been suggested as a promising solution for future multicore systems. In this talk, we plan to address the concept of ¿network¿ in multiprocessor systems-on-chip and identify specific design principles and optimization techniques that are relevant to our research community. More precisely, we plan to discuss fundamental mathematical techniques that can be used to design, control, and optimize such networks in a rigorous manner at nanoscale. At the same time, we plan to also highlight alternatives to the conventional paradigm of network design. This new vision is based on rigorous developments in the field of statistical physics and information theory that allow us to model the network as a thermodynamical system. The hope is that this new modeling paradigm can enable not only capturing the intrinsic interactions among various network components, but also developing powerful techniques for predicting and optimizing the on-chip network behavior.
Keywords :
integrated circuit interconnections; integrated circuit modelling; network-on-chip; NoC; bus-based communication; communication architecture design; design space exploration; energy consumption; identify specific design principles; information theory; mathematical techniques; multicore systems; multiprocessor systems-on-chip; network-on-chip architecture; network-on-chip design; optimization techniques; statistical physics; Communication system control; Computer architecture; Costs; Design optimization; Energy consumption; Multicore processing; Network-on-a-chip; Power system interconnection; Power system modeling; Space exploration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Network on Chip Architectures, 2009. NoCArc 2009. 2nd International Workshop on
Conference_Location :
New York, NY
Print_ISBN :
978-1-60558-774-5
Type :
conf
Filename :
5375720
Link To Document :
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