DocumentCode :
510452
Title :
40 Gbit/s on-off-keyed system with 5.71 GHz clock recovery circuit using duty cycle division multiplexing
Author :
Mahdiraji, G. Amouzad ; Malekmohammadi, A. ; Abas, A.Fauzi ; Abdullah, M.Khazani
Author_Institution :
Department of Computer and Communication Systems Engineering, University Putra Malaysia, 43400 Serdang, Selangor, Malaysia
fYear :
2009
fDate :
2-6 Nov. 2009
Firstpage :
1
Lastpage :
2
Abstract :
We show the realization of 40 Gbit/s on-off-keyed system that can be recovered at 5.71 GHz clock using duty cycle division multiplexing technique with the receiver sensitivity of −22.1 dBm.
Keywords :
Circuits; Clocks; OFDM; Optical filters; Optical modulation; Optical receivers; Optical sensors; Sampling methods; Time division multiplexing; Wavelength division multiplexing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications and Photonics Conference and Exhibition (ACP), 2009 Asia
Conference_Location :
Shanghai, China
Print_ISBN :
978-1-55752-877-3
Electronic_ISBN :
978-1-55752-877-3
Type :
conf
Filename :
5377113
Link To Document :
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