Title :
Carbon nanotube bundles as nanoscale chip to package interconnects
Author :
Chiariello, Andrea G. ; Miano, Giovanni ; Maffucci, Antonio
Author_Institution :
Dipt. di Ing. Elettr., Univ. di Napoli Federico II, Naples, Italy
Abstract :
The paper presents recent advances in carbon nanotube interconnect modeling, with focus on their application to nanoscale chip packaging. An enhanced electrical model of carbon nanotube bundles is used, able to take into account the effects of different nanotube sizes covered by this application. The use of carbon nanotubes as chip to package interconnects at nanoscale dimensions is analyzed and the electrical parasitics introduced by these interconnects are compared to those predicted by other packaging technologies.
Keywords :
carbon nanotubes; chip scale packaging; interconnections; nanoelectronics; nanotube devices; C; carbon nanotube bundles; carbon nanotube interconnect modeling; electrical parasitics; enhanced electrical model; nanoscale chip packaging; nanoscale dimensions; Carbon nanotubes; Copper; Current density; High K dielectric materials; Integrated circuit interconnections; Nanoelectronics; Nanoscale devices; Nanostructured materials; Packaging; Thermal conductivity; carbon nanotubes; nanopackaging;
Conference_Titel :
Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on
Conference_Location :
Genoa
Print_ISBN :
978-1-4244-4832-6
Electronic_ISBN :
1944-9399
