DocumentCode :
511406
Title :
Repair techniques for hybrid Nano/CMOS computational architecture
Author :
Srivastava, Saket ; Melouki, Aissa ; Al-Hashimi, Bashir M.
Author_Institution :
Sch. of Electron. & Comput. Sci., Univ. of Southampton, Southampton, UK
fYear :
2009
fDate :
26-30 July 2009
Firstpage :
198
Lastpage :
201
Abstract :
Presence of high defect rate in nanofabrics due to the inadequate fabrication processes has held back the development of emerging technology architecture. In this work, we propose two repair techniques to provide high level of defect tolerance in lookup table (LUT) based Boolean logic approach implemented in nano/CMOS. Further, we demonstrate that direct application of memory repair techniques is ineffective in dealing with high defect rate in hybrid nano/CMOS architecture. We show that the proposed techniques are capable of handling more than 20% defect rate in hybrid nano/CMOS architecture with efficient utilization of spare units.
Keywords :
Boolean algebra; CMOS integrated circuits; electronic engineering computing; nanoelectronics; table lookup; LUT based Boolean logic approach; defect tolerance; hybrid nano-CMOS computational architecture; lookup table; Boolean functions; CMOS logic circuits; CMOS memory circuits; CMOS process; CMOS technology; Computer architecture; Computer interfaces; Error correction codes; Table lookup; Tagging;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on
Conference_Location :
Genoa
ISSN :
1944-9399
Print_ISBN :
978-1-4244-4832-6
Electronic_ISBN :
1944-9399
Type :
conf
Filename :
5394597
Link To Document :
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