Nanoscale reconfigurable computing using non-volatile 2-D STTRAM array

In this paper, we investigate the combination of a novel computing paradigm referred to as Memory Based Computing (MBC) and an emerging non-volatile nanoscale memory technology, namely Spin-Torque Transfer Random Access Memory (STTRAM), to build a reconfigurable nanocomputing framework with high integration density, robustness and energy-delay efficiency. MBC uses a 2-D memory array as underlying computing element. Noting the read-dominant access pattern in MBC, we optimize the STTRAM cells to increase the energy-delay efficiency. Further, exploiting the asymmetric nature of the cells, we introduce the notion of preferential storage which optimizes the cell performance for `1´ over `0´ and skew the LUT content toward `1´ for improved energy-delay product (EDP).