Title :
Impact of process variation on NASIC nanoprocessors with 2-way redundancy
Author :
Leuchtenburg, Michael ; Narayanan, Pritish ; Wang, Teng ; Moritz, Csaba Andras
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of Massachusetts, Amherst, MA, USA
Abstract :
Process variation is expected to persist in the various novel nanoscale fabrics being proposed to replace CMOS. Logic circuits built using non-traditional and bottom-up techniques will need to meet new design rules, such as tolerance of high defect rates and use of regular structures in layout. One circuit fabric type that meets these requirements is grid-based logic, with built-in fault resilience provided by 2-way redundancy. In this work, we show that this fabric design also is able to tolerate substantial process variation in addition to its defect resistance.
Keywords :
application specific integrated circuits; fault tolerance; logic design; nanoelectronics; redundancy; 2-way redundancy; CMOS; NASIC nanoprocessors; bottom-up techniques; built-in fault resilience; grid-based logic; logic circuits; nanoscale fabrics; nontraditional techniques; process variation; CMOS logic circuits; CMOS process; Circuit faults; Fabrics; Logic circuits; Manufacturing processes; Redundancy; Resilience; Testing; Timing;
Conference_Titel :
Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on
Conference_Location :
Genoa
Print_ISBN :
978-1-4244-4832-6
Electronic_ISBN :
1944-9399
