Threshold-voltage variations effects on the reliability of nano-scale CMOS logic gates

The reliability of nano-scale devices and circuits has received revived attention in recent years. This paper focuses on the reliability at the gate level considering the variations of devices parameters. In particular, this study aims to quantify the effects of threshold voltage variations on the reliability of nanometer-scale CMOS logic gates. The reliability is quantified in terms of the probability-of-failure of individual gates, which is obtained from extensive Monte Carlo simulations of CMOS gates. The study considers the NAND-2 and majority-3 gates at 90 nm and 22 nm, and compares the effects of threshold voltage variations on the reliability of each gate. The results show a clear dependency pattern of reliability on the gate´s input combinations.