A link failure aware routing algorithm for Networks-on-Chip in nano technologies

As nanotechnology scales down, the reliability issues are becoming more crucial, especially for Network-on-Chip (NoC) which must provide the communication requirements of Multi-Processor System-on-Chip (MP-SoC) even in presence of faults. In this paper we present a low cost faulty-link-tolerant routing algorithm through dynamic reconfiguration when the regular mesh topology is altered by faulty links. This algorithm is a reconfigurable extension of deterministic routing algorithms and is deadlock free by prohibiting a few turns. The performance and total energy consumption overheads which are very small under the low loads are evaluated through appropriate simulations.