ILP-based optimal multi-threshold voltages assignment under performance constraints

The reduction of leakage power has become a more and more important issue in deep sub-micron VLSI low power design. In this paper, we implement a multi threshold voltage optimization methodology for low leakage power. The objective is to minimize the leakage power consumption of the combinational circuit and under various critical path timing constraints. After circuit static timing analysis, we formulate corresponding circuit power and timing model, and then solve the problem by using the integer linear programming (ILP)-based method. For the ILP formulations, the commercial tool LINGO is used to get the optimized result. All benchmark circuits are realized with TSMC 90 nm library. Experimental results indicate that multi-threshold voltage approach can provide up to 45.40% average leakage reduction by comparing to original design, and average runtime can achieve 21 seconds.